In advanced semiconductor memory manufacturing, the feature size keeps aggressively shrinking, creating problems in the fabrication process and leading to decreasing yield. Three key factors that can impact memory process and yield are lithographic process window, full field CD uniformity (CDU), and correction run time performance. In this paper, we describe and present a mask processing technique utilizing a) global array detect (GAD) for detecting and optimizing cell repetition, b) periodic boundary condition (PBC) for preserving simulation and mask symmetry, and c) cell-level ILT (CLILT) flow to process repeated cell regions and blend various design parts. With GAD + PBC + CL-ILT processing, we can achieve a perfectly consistent mask array region with enlarged process window and minimum local CD variation for a full field mask. Moreover, with fewer pattern units (called templates) to process, we can complete full chip ILT with reasonable time and compute resources compared to OPC full chip correction. In this paper, we show simulation and wafer print results including pattern fidelity, process window, mask consistency, and run time data.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.