Mr. Moydul Islam Profile

Moydul Islam

at Micron Technology Inc

SPIE Involvement:

Author

Publications (1)

This will count as one of your downloads.

You will have access to both the presentation and article (if available).

DOWNLOAD NOW

This content is available for download via your institution's subscription. To access this item, please sign in to your personal account.

Email or Username Forgot your username?

Password Forgot your password?

Show

Keep me signed in

No SPIE account? Create an account

Proceedings Article | 20 March 2019 Paper

Full-chip layout optimization for photo process window improvement of 3D NAND metal routing level

Jennefir Digaum, Hung-Eil Kim, Eric Christensen, Hamilton Sanchez, Moydul Islam

Proceedings Volume 10962, 109620K (2019) https://doi.org/10.1117/12.2512567

KEYWORDS: Metals, Electroluminescence, Critical dimension metrology, Optical proximity correction, Optical lithography, Printing, Reticles, Finite element methods, Transition metals, Semiconducting wafers

Read Abstract +

The continuous scaling of 3D NAND by vertically stacking more tiers in a single die presents some major challenges . One of these challenges is the effect of increasing surface topography on photolithography. Although photolithography is relaxed in 3D NAND process compared to 2D NAND, surface topography can lead to a reduced process window (PW) of critical immersion levels. For a metal routing level near the top of the die stack, up to ~240 nm of topography can be present at immersion photolithography levels. In tight pitch regions of the metal routing layout, topography variations can cause poor printing, particularly near locations where the metal routing bends due to various layout constraints. Edge progression and corner jog layout optimization provide a solution to this less-discussed challenge in the 3D NAND fabrication process. Simulation results show a 70% increase of the PW in the areas where edge progression was applied. In bending regions of the metal routing, jog optimization improves the PW by 40%. These two layout optimization techniques increased the overall metal routing PW by ~40%, and this increase was validated by wafer FEM data. Additionally, the same jog optimization and edge progression techniques can be used to fix hot spot areas due to process variations. This paper presents a solution to compensate for the decreased PW of the metal routing level near the top of a 64-tier 3D NAND die due to fab topography issues through corner jog and edge progression layout optimization.

My Library

You currently do not have any folders to save your paper to! Create a new folder below.

Folder Name

Folder Description

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks. You are receiving this notice because your organization may not have SPIE eBooks access.*

*Shibboleth/Open Athens users─please sign in to access your institution's subscriptions.

To obtain this item, you may purchase the complete book in print or electronic format on SPIE.org.

ORGANIZATIONAL
Sign in with credentials provided by your organization.

Organizational Username

Organizational Password

Show/Hide Password

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members:

Non-members: ADD TO CART

Keywords/Phrases

Search In:

Publication Years