We present a glitch propagation model that can be used to categorize the propagation likelihood of a given noise
waveform trough a logic gate. This analysis is key to predict if a SET induced within a combinational block is capable of
causing a SEU. The model predicts the glitch output characteristics given the input noise waveform for each gate in a 65-
nm technology library. These noise transfer curves are fitted to known functions to have a simple analytical equation and
compute the propagation. Comparison between simulations and model shows a good agreement.
Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits
at deep sub-micron dimensions even at ground level. To face this challenge, a designer must dispose of a variety of
mitigation schemes adapted to their specific design constraints. Built In Current Sensors have been proposed as a
detection scheme for single event upsets in SRAM. In this paper, Power-Bus current transients in SRAM memories for
Single Event Upset Detection have been analyzed in a 65nm CMOS technology. The different types of current roles
which are applied during the simulation is discussed. The results show the important contribution of leakage currents in
the response of the memory cell to an external event.
KEYWORDS: Transistors, Switching, Logic devices, Field effect transistors, CMOS technology, Reliability, Logic, Very large scale integration, Temperature metrology, Capacitors
CMOS IC scaling has surpassed the 100nm barrier being now in the 65nm node with a rapid migration to the 35nm generation. In achieving the primary goals of technology scaling such as performance and density increase at a reduced cost per transistor, new side effects must be solved representing further challenges to the advance of the predicted roadmap. One of these challenges is related to the management of thermal-related effects such as hot-spots and overall junction temperature increase as they may have a significant impact on performance, power containment, circuit reliability, and even functionality. The adoption of adequate thermal management solutions requires a detailed analysis of the fundamental relationships governing the device and interconnect subsystem. Although much attention has been given to such analysis at the device and the logic inverter levels, less is known about such dependences in complex gates with transistor stacks. In this work we study the fundamental mechanisms underlying the temperature dependence of transistor stacks showing the key role of the stack dynamic threshold on the overall delay-temperature behavior at the gate level.
KEYWORDS: Transistors, Tolerancing, Analog electronics, Bridges, Amplifiers, Signal processing, Oscillators, Capacitance, Oscilloscopes, Mixed signal circuits
This paper experimentally analyses the capabilities of an Oscillation-Based Test technique for diagnosis purposes. To evaluate the feasibility of this test strategy, the technique is applied to an Operational Transconductance Amplifier with fault injection capabilities. The application of this methodology has low impact on circuit performances. Voltage and current magnitude have been considered as test observables. The effects of catastrophic and parametric defects (bridges, opens and shorts) are analyzed in this work. Results show that by a right choice of the test observable, this technique provides high fault coverage levels even in the case of process variations.
The performance increase of VLSI circuits is leading to increase power dissipation and operation temperature, consequently management of thermally related issues is rapidly becoming one of the most challenging efforts in high performance IC design. Within die temperature gradients on silicon can occur due to different activity maps and in high performance ICs differences as high as 50 °C can be achieved during normal operation. Clock network constitutes one of the most critical elements in synchronous circuits and has a significant impact on speed, area and power dissipation. Due to the well-known impact of temperature on delay, the effect of non-uniform thermal maps on the clock skew can acquire a significant relevance. In this work we analyze the impact of within die thermal gradients on the clock skew considering the dependence on temperature on both active devices and interconnects.
Today, the use of robots for self acting tasks in applications ranging from biology and medicine to microsystems technology demand miniaturized dimensions and high-precision handling techniques. A lot of these tasks have been carried out by humans, but the manual capabilities are restricted to certain tolerances. Transport and manipulation of biological cells or assembly of micromechanical parts are the best suited applications for microrobots with sizes about cm3. Low cost and high-resolution actuators are critical performances which determine to choose piezoceramic materials as more suitable for micropositioning and micromanipulation units of a cm3 microrobot. Smart Piezoactuator Unit (SPUs) as a basic element of a new generation of cm3 microrobots have been developped. The main characteristic of this proposed Smart Piezoactuator Unit system is the integration of driving circuitry with the piezoelectric actuators and to include a serial communication interface to minimize the number of power and command wires. Micropositioning and micromanipulation units are developed combining properly 6 Smart Piezoactuator Units each one. A BCD technology (Bipolar, CMOS, DMOS) is used to design high voltage smart power integrated circuit for these Smart Piezoactuator Units. Using this technology we integrate in the same chip 4 power drivers with its control and protection circuitry.
A magnetic field-to-voltage converter using a magnetic MOSFET devices has been designed, simulated and tested. The resulting sensor was measured under magnetic fields ranging from 0 to 0.8T, the obtained sensitivity was 0.03T-1 with an offset lower than 0.2 percent. SPICE macro model for the MAGFET in the saturation region is presented. Also, we have simulated the behavior of the specific A/D system, based on a current-mode technique, making use of high description language.
Pressure sensors structures have been fabricated in a commercial CMOS foundry technology using a post-processing for back-side wafer micro machining. In order to predict the sensor response to an externally applied differential pressure, the structure behavior has been simulated by Finite Element Methods. The design and fabrication of test structures for these sensor devices is described. Experimental results obtained using these structures are presented.
Implementation and test results of an array for image applications with full-frame analog memory is presented. The array was implemented using 1.0 micrometers double metal, single poly n-well standard CMOS technology. The sensor consists of a 24 by 24 pixels square array and circuitry for random access readout. A pixel is composed by a phototransistor and control circuitry to regulate the exposure time to light of phototransistors. Each pixel also includes an analog memory implemented using MOSFET capacitors. The output buffer drives the capacitance of the output line. The system requires a total core area of 5 mm2. Tests were performed for each individual pixels and for the complete array. The voltage output as a function of integration time under different illumination levels shows a linear behavior. Varying the exposure time is possible to change the detector sensitivity. The fixed pattern noise was 0.58 percent of saturation level. Memory capabilities were also tested, allowing non-destructive reading and a storage time over few seconds without a significant degradation.
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