CONFERENCE PROCEEDINGS
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Taichi Koizumi
at Semiconductor Co
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Publications (3)
Proceedings Article | 23 March 2011 Paper
Mask enhancer technology with source mask optimization (SMO) for 2Xnm-node logic layout gate fabrication
Takashi Matsuda, Shigeo Irie, Tadami Shimizu, Takashi Yuito, Yasuko Tabata, Yuuji Nonami, Akio Misaka, Taichi Koizumi, Masaru Sasago
Proceedings Volume 7973, 797316 (2011) https://doi.org/10.1117/12.878727
KEYWORDS: Photomasks, Source mask optimization, Binary data, Halftones, Logic devices, Lithographic illumination, Phase shifts, Resolution enhancement technologies, Logic, Optical proximity correction
Proceedings Article | 13 March 2010 Paper
Mask enhancer technology for sub-100nm pitch random logic layout contact hole fabrication
Takashi Yuito, Hiroshi Sakaue, Takashi Matsuda, Tadami Shimizu, Shigeo Irie, Fumio Iwamoto, Akio Misaka, Taichi Koizumi, Masaru Sasago
Proceedings Volume 7640, 76401B (2010) https://doi.org/10.1117/12.848025
KEYWORDS: Photomasks, Printing, Lithography, Image enhancement, Logic, Transmittance, Lab on a chip, Resolution enhancement technologies, Immersion lithography, Phase shifts
Proceedings Article | 22 May 1995 Paper
CD control using latent image for lithography
Taichi Koizumi, Takahiro Matsuo, Masayuki Endo, Masaru Sasago
Proceedings Volume 2439, (1995) https://doi.org/10.1117/12.209226
KEYWORDS: Critical dimension metrology, Lithography, Silicon, Excimer lasers, Image processing, Photoresist processing, Control systems, Photoresist materials, Atomic force microscope
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