A critical challenge in semiconductor manufacturing is the high electricity consumption, especially by lithography tools, which significantly contribute to the industry's environmental impact. For lithography track systems, reducing the energy consumption of hotplate processes is essential due to their high energy demands. This study introduces an innovative, energy-efficient process that offers a viable alternative to conventional thermal crosslinking systems for Spin-On Carbon (SOC) and spin-on glass (SOG) underlayers, which typically require high temperatures for full film densification. The proposed method utilizes an overall-wafer optical exposure system, integrated on SCREEN’s DT-3000 track, to crosslink underlayer materials designed by Brewer Science to cure through light exposure. This paper demonstrates how this optical crosslinking approach can achieve substantial energy savings of 85% for SOC and 60% for SOG, while maintaining lithographic performance. The transition from a traditional hotplate process to a light-curing mechanism is thoroughly examined from multiple perspectives.
As the awareness of climate change and sustainability grows, industries are placing more commitment to reduce their environmental footprint. Semiconductor companies are no exception, and many are now working to reduce their greenhouse gas (GHG) emissions and adopt greener practices as crucial steps towards a more environmentally responsible future. Amongst the top sustainability challenges faced in semiconductor manufacturing, electricity consumption emerges as a critical concern, with lithography tools requiring a substantial amount of energy to operate. As a track vendor, reducing energy consumption and optimizing tool efficiency are ongoing challenges at SCREEN, where hotplate processes rank amongst the most energy-intensive operations, especially during the bake of underlayer materials that require high temperatures to achieve full film densification. This paper shows an innovative energy-efficient process as a viable alternative to conventional spin-on carbon (SOC) and spin-on glass (SOG) thermal crosslinking systems. We deeply explore the feasibility to use an overall-wafer exposure system integrated on SCREEN’s DT-3000 track to harden underlayer materials specifically designed to crosslink via light, without the need of heat. We demonstrate how migration from a hotplate process to a 100% optical curing mechanism can lead to outstanding savings in energy and process time, while keeping the lithographic performance.
In the ever-evolving landscape of semiconductor manufacturing, ensuring impeccable process stability and defect control remains crucial in modern lithography. These elements have driven the maturation of the entire extreme ultraviolet (EUV) lithography ecosystem, which is now geared to meet the upcoming challenges. A critical component of this ecosystem is the lithography track, whose performance capabilities have been evolving rapidly to keep pace with technology roadmap advancements. In this study, we present the capabilities of novel hardware solutions integrated into SCREEN's DT-3000 coat-develop track system when applied to metal oxide resist (MOR) platforms. We demonstrate how hardware development remains a fundamental driver for enhancing not only process stability and defect control but also for optimizing additional critical metrics such as resolution, line width roughness (LWR), defect-free window, and pattern shape. These advancements underscore the continued importance of hardware innovation in the semiconductor manufacturing landscape and its indispensable role in supporting the transition to high-NA EUVL technology, ensuring high-quality and reliable production.
The next generation of this technology (using a high-numerical aperture (NA) at 0.55 compared to the present at 0.33) is also currently being prepared and is scheduled to be production ready within the next few years. However, it is well known that the application of higher NA will lead to smaller depth of focus (DOF). The DOF with NA 0.55 systems will reduce to 1/3 of the value that we have in current 0.33 NA systems, i.e. if DOF at NA 0.33 is 100nm then at NA 0.55, DOF will be around 30 to 40nm. At these exposure conditions, wafer surface distortions as an effect of backside defects will become significant concern. In this study, the wafer backside at exactly the same locations detected as where these abnormal CD’s were detected on wafer frontside. And the evidence was shown that the backside defects affected to frontside pattern deformation. Furthermore, it was found that an effective backside cleaning process can mitigate pattern defocus caused by these wafer backside particles.
The microchip fabrication process consists of hundreds of steps, where each step can contribute to the backside contamination of the wafer. When clamping a wafer in the exposure tool, the presence of backside defects can lead to various issues, including local deformation of the wafer or clamping distortions, that result in focus loss or on-product overlay drifts in that area. With device scaling and the introduction of High NA EUV, we anticipate backside defects to be a more severe problem for frontside patterns. The lenses of 0.55 NA EUV systems will have a very small depth of focus compared to 0.33 NA EUV scanners, meaning that a defect present on the wafer backside can easily translate into frontside pattern failures. Additionally, backside contamination increases the risk of damage to the scanner wafer-table (WT) having a negative impact on its lifetime, maintenance cost and productivity. In this work, to better understand the impact of backside contamination on the EUV patterning performance, a new characterization approach was set up based on an optical inspection technique, Pattern Shift Response PSR. Together with SCREEN, we could demonstrate a good correlation between backside contamination, detected by the levelling measurements from the NXE3400B, and frontside pattern distortions. Additionally, the impact of backside contamination on wafer CD uniformity was investigated by measuring CD across. We confirmed that by using more robust cleaning techniques we were able to reduce the number of backside defects and increase wafer yield.
As technology advances, the need for precise and reliable track systems became crucial to enable high-performance and reliable semiconductor manufacturing. Progressive track development boosts several metrics like defectivity, critical dimension uniformity (CDU), line width roughness (LWR) and pattern shape. In this work, we investigate and improve the defect levels for different EUV resist platforms using SCREEN’s DT-3000 coat-develop track system. Additionally, we showcase the recent advancements on DT-3000 track to improve CD uniformity, a metric that plays a vital role in EUVL as it ensures consistent and precise dimensions printed on the chips. Through an innovative post-exposure bake hotplate design, we introduce a pioneer solution to correct process fingerprints that affect the CD stability across the wafer, thus meeting the challenging demands of advanced generation semiconductor manufacturing.
While several leading semiconductor manufacturers are already heavily investing in the development of high-NA EUV technology, there are still some technical challenges to overcome. Photoresists are identified as main drivers to achieve the required ultimate resolution, with the development of new EUV materials being ranked as one of the top priorities to address. Currently, MOR is the primary candidate for patterning at 0.55NA relevant pitches, but stability still must be demonstrated. The aim of this work was to extend the current knowledge about the impact of delay effects on resist stability. The effect of post-coating, post-exposure and post-PEB delay on litho performance were thoroughly analyzed and compared for metal oxide and main-chain scission resist platforms. It has been observed that for both chemistries, track stand-alone processing might be a possible and effective approach to explore towards high-NA, bringing more flexibility and enabling higher throughput.
Control of wafer backside defectivity is a challenge during the chip manufacturing process and has been extensively investigated throughout the past decade, especially on immersion lithography systems. As technology nodes continue to scale down and we approach the high NA EUV lithography era, backside contamination is becoming a critical problem. High NA EUV exposure systems have a smaller depth of focus compared to low NA EUV systems. The presence of backside wafer defects can easily lead to focus loss or on-product overlay errors leading to pattern failures. To anticipate the upcoming challenges, SCREEN has developed a sophisticated track-integrated backside cleaning (BSC) module on the DT-3000 system. This enables an advanced post-coating BSC solution directly before exposure. Together ASML, imec and SCREEN, investigated the potential of this unique BSC process to extend the lithographic performance of EUV material stacks, by correlating backside contamination with frontside patterning performance and the minimization of scanner focus spots. With this approach, we try to identify and characterize potential backside defect killers that could cause not only yield loss, but also physical deterioration of the scanner wafer table (WT) and its lifetime.
As technology nodes continue to scale down, the full ecosystem around Extreme Ultraviolet Lithography (EUVL) is becoming more mature and proactive in the anticipation of upcoming challenges. To keep up with the technology roadmap evolution, lithography track performance capabilities have also been rapidly expanding through the years and new modules are being specially designed to support the lithographic performance improvement of different materials. In this work, we showcase the capability of novel hardware solutions currently available on SCREEN’s DT-3000 coat-develop track system. Based on a holistic approach, we demonstrate how hardware development is still a key not only to improve process stability and drive down defectivity to historically low levels but also to boost other metrics such as line width roughness (LWR), defect-free process window, and pattern shape.
The use of a 4F2 cell configuration which enables higher densification is common in emerging memory devices. The pitch scaling and the robustness of these devices mainly rely on the patterning of the orthogonal array vertical pillar process. In this paper, we screen several lithography process approaches to optimize the 40nm pitch pillar patterning using single exposure EUV (extreme ultraviolet) lithography. The results show that with the optimized 40nm pitch process roughly 0.6nm 3-Sigma WCDU (wafer critical dimension uniformity) and 1.4nm 3-Sigma LCDU (local critical dimension uniformity) can be obtained post-litho for 21.1nm mean CD (critical dimension). Post-etch patterning with the best process shows 1.8nm 3-Sigma WCDU and 1.3nm 3-Sigma LCDU at 17.2nm mean CD. Smaller pitches have also been explored to identify the limits of the single EUV lithography process. Structures at 34nm pitch have shown high amount of pillar collapse. For 36nm pitch, on the other hand, a reasonable litho performance could be obtained with slightly boosted CD. The post-litho results show that with the optimized 36nm pitch process 0.4nm 3-Sigma WCDU and 1.4nm 3-Sigma LCDU can be obtained for 19.1nm mean CD.
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