Dr. Zhibin Yu Profile

Dr. Zhibin Yu

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Proceedings Article | 26 June 2023 Paper

An automatic QoS-aware resource partitioning framework for cloud environment

Bingwei Chen, Jianquan Li, Bozhong Liu, Zhibin Yu

Proceedings Volume 12721, 127210W (2023) https://doi.org/10.1117/12.2683456

KEYWORDS: Computer hardware, Cloud computing, Machine learning, Design and modelling, Mathematical optimization

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The increasing use of computers in various fields has led to the popularization of cloud computing due to its advantages, such as large scale, high performance, low power consumption, high reliability, and low cost. However, the rapid growth of business volume and kinds of computer hardware resources, along with complex computer architecture, poses challenges in allocating hardware resources. Traditional methods struggle to meet the varying requirements of different businesses, hinder automatic tuning, and limit the improvement of overall system performance. In this regard, we propose an automatic QoS-aware resource partitioning framework that aims to maximize the overall performance of the system. Our contributions include an automatic performance tuning framework for cloud environments, a Deep Q-learning Network (DQN) based performance optimization method, and achieving a speed-up of at most 1.73 times compared to uniform partitions for CPU overload scenarios involving throughput-aware and latency-critical workloads. The proposed framework addresses the challenges faced by cloud computing by adopting different allocation methods for hardware resources that maximize performance in different application scenarios. The framework efficiently utilizes emerging hardware resource control capabilities to improve hardware and system performance. The use of DQN in performance optimization allows the framework to learn from past experiences and adapt to different situations, resulting in better resource allocation decisions. The proposed framework can significantly reduce the waste of resources and unnecessary expenditures for governments and enterprises. Our framework can serve as a guide for future research in cloud computing and related fields.

Proceedings Article | 11 November 2022 Paper

FPGA-based regular expression matching acceleration system design and implementation

Jianquan Li, Bingwei Chen, Liang Gu, Zhibin Yu

Proceedings Volume 12348, 123483R (2022) https://doi.org/10.1117/12.2641474

KEYWORDS: Field programmable gate arrays, Data transmission, Network security, Data conversion, Clocks, Inspection, Computing systems, Structural design, Lithium, Internet

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The Internet environment is becoming more and more complex with the increasing scale of users and richness of network applications recent years. Malicious network flows are difficult to be inspected with only five-tuple information contained in the network packet header, and application layer traffic analysis has become an important basis for network security. Deep packet inspection (DPI) is an application layer-based flow monitoring and identification technology, which inspects and analyzes each network data packet through a regular expression matching system to check the compliance and security of network data packets. However, with the continuous increment of Internet bandwidth, limited by the computing capability of the processor and the computational complexity of regular expressions, the content recognition subsystem based on the central processing unit (CPU) is hard to identify malicious network flows in a high-speed network environment with large traffic so that the regular expression matching system became a bottleneck in network security. A filed programmable gate array (FPGA)-based regular expression matching acceleration system with high computing parallelism is proposed this paper. And the regular expressions are converted into state transition tables and transferred into Verilog HDL through lexical analysis. The data throughput and development efficiency are rapidly improved with innovation design upon hardware structure and compilation tools. The function and performance of the system were verified with simulation software and it is proved that the throughput of the system based on Xilinx Alevo U200 acceleration card will reach at over 50Gbps under condition that more than 10,000 regular expressions with thirtytransition-state implemented. This work will greatly improve the entire performance of the firewall and shorten the system iteration and upgrade cycle.

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