Lithography

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

[+] Author Affiliations
Ioannis Karageorgos, Wim Dehaene

imec, Kapeldreef 75, Leuven B-3001, Belgium

KU Leuven, Department of Electrical Engineering (ESAT), Kasteelpark Arenberg 10, Leuven B-3001, Belgium

Julien Ryckaert, Roel Gronheid, Kris Croes, Joost Bekaert, Geert Vandenberghe, Michele Stucchi

imec, Kapeldreef 75, Leuven B-3001, Belgium

Maryann C. Tung, H.-S. Philip Wong

Stanford University, Department of Electrical Engineering, 420 Via Palou, Stanford, California 94305, United States

Evangelos Karageorgos

University of Athens, Department of Informatics and Telecommunications, Panepistimiopolis, Athens 15784, Greece

J. Micro/Nanolith. MEMS MOEMS. 15(4), 043506 (Nov 07, 2016). doi:10.1117/1.JMM.15.4.043506
History: Received September 18, 2016; Accepted October 13, 2016
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Abstract.  Major advancements in the directed self-assembly (DSA) of block copolymers have shown the technique’s strong potential for via layer patterning in advanced technology nodes. Molecular scale pattern precision along with low cost processing promotes DSA technology as a great candidate for complementing conventional photolithography. Our studies show that decomposition of via layers with 193-nm immersion lithography in realistic circuits below the 7-nm node would require a prohibitive number of multiple patterning steps. The grouping of vias through templated DSA can resolve local conflicts in high density areas, limiting the number of required masks, and thus cutting a great deal of the associated costs. A design method for DSA via patterning in sub-7-nm nodes is discussed. We present options to expand the list of usable DSA templates and we formulate cost functions and algorithms for the optimal DSA-aware via layout decomposition. The proposed method works a posteriori, after place-and-route, allowing for fast practical implementation. We tested this method on a fully routed 32-bit processor designed for sub-7 nm technology nodes. Our results demonstrate a reduction of up to four lithography masks when compared to conventional non-DSA-aware decomposition.

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© 2016 Society of Photo-Optical Instrumentation Engineers

Citation

Ioannis Karageorgos ; Julien Ryckaert ; Roel Gronheid ; Maryann C. Tung ; H.-S. Philip Wong, et al.
"Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits", J. Micro/Nanolith. MEMS MOEMS. 15(4), 043506 (Nov 07, 2016). ; http://dx.doi.org/10.1117/1.JMM.15.4.043506


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