Improved CD control for 45-40 nm CMOS logic patterning: anticipation for 32-28 nm

Bertrand Le Gratiet; Frank Sundermann; Jean Massin; Marianne Decaux; Nicolas Thivolle; Fabrice Baron; Alain Ostrovsky; Cedric Monget; Jean Damien Chapon; Yoann Blancquaert; Karen Dabertrand; Lionel Thevenon; Benedicte Bry; Nicolas Cluet; Bertrand Borot; Raphael Bingert; Thierry Devoivre; Pascal Gourard; Laurène Babaud; Ute Buttgereit; Robert Birkner; Mark Joyner; Erez Graitzer; Avi Cohen

doi:10.1117/12.845987

1 April 2010 Improved CD control for 45-40 nm CMOS logic patterning: anticipation for 32-28 nm

Bertrand Le Gratiet, Frank Sundermann, Jean Massin, Marianne Decaux, Nicolas Thivolle, Fabrice Baron, Alain Ostrovsky, Cedric Monget, Jean Damien Chapon, Yoann Blancquaert, Karen Dabertrand, Lionel Thevenon, Benedicte Bry, Nicolas Cluet, Bertrand Borot, Raphael Bingert, Thierry Devoivre, Pascal Gourard, Laurène Babaud, Ute Buttgereit, Robert Birkner, Mark Joyner, Erez Graitzer, Avi Cohen

Author Affiliations +

Proceedings Volume 7638, Metrology, Inspection, and Process Control for Microlithography XXIV; 76380A (2010) https://doi.org/10.1117/12.845987
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

Since 2008, we have been presenting some papers regarding CMOS 45nm logic gate patterning activity to reduce CD dispersion. After a global CD budget evaluation at SPIE08, we have been focusing on Intrafield CD corrections using Dose Mapper^TM. The story continues and since then we have pursued our intrafield characterisation and focus on ways to get Dose Mapper^TM dose recipe created before the first silicon is coming. In fact 40nm technology is already more demanding and we must be ready with integrated solutions for 32/28nm node. Global CD budget can be divided in Lot to Lot, Wafer to Wafer, Intra wafer and Intra field component. We won't talk here about run to run solutions which are put in place for Lot to Lot and Wafer to Wafer. We will emphasize on the intrafield / intrawafer process corrections and outline process compensation control and strategy. A lot of papers regarding intrafield CD compensation are available in the litterature but they do not necesserally fit logic manufacturing needs or possibilities. We need to put similar solutions in place which are comprehensive and flexible. How can we correct upfront an Etch chamber CD profile combined with a mask and scanner CD signature? How can we get intrafield map from random logic devices? This is what we will develop in this paper.

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Bertrand Le Gratiet, Frank Sundermann, Jean Massin, Marianne Decaux, Nicolas Thivolle, Fabrice Baron, Alain Ostrovsky, Cedric Monget, Jean Damien Chapon, Yoann Blancquaert, Karen Dabertrand, Lionel Thevenon, Benedicte Bry, Nicolas Cluet, Bertrand Borot, Raphael Bingert, Thierry Devoivre, Pascal Gourard, Laurène Babaud, Ute Buttgereit, Robert Birkner, Mark Joyner, Erez Graitzer, and Avi Cohen "Improved CD control for 45-40 nm CMOS logic patterning: anticipation for 32-28 nm", Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 76380A (1 April 2010); https://doi.org/10.1117/12.845987

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