Gate double patterning strategies for 10nm node FinFET devices

Hubert Hody; Vasile Paraschiv; David Hellin; Tom Vandeweyer; Guillaume Boccardi; Kaidong Xu

doi:10.1117/12.2045647

28 March 2014 Gate double patterning strategies for 10nm node FinFET devices

Hubert Hody, Vasile Paraschiv, David Hellin, Tom Vandeweyer, Guillaume Boccardi, Kaidong Xu

Proceedings Volume 9054, Advanced Etch Technology for Nanopatterning III; 905407 (2014) https://doi.org/10.1117/12.2045647
Event: SPIE Advanced Lithography, 2014, San Jose, California, United States

Abstract

Amorphous silicon (a-Si) gates with a length of 20nm have been obtained in a ‘line & cut’ double patterning process. The first pattern was printed with EUV photoresist and had a critical dimension close to 30nm, which imposed a triple challenge on the etch: limited photoresist budget, high line width roughness and significant CD reduction. Combining a plasma pre-etch treatment of the photoresist with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

Citation Download Citation

Hubert Hody, Vasile Paraschiv, David Hellin, Tom Vandeweyer, Guillaume Boccardi, and Kaidong Xu "Gate double patterning strategies for 10nm node FinFET devices", Proc. SPIE 9054, Advanced Etch Technology for Nanopatterning III, 905407 (28 March 2014); https://doi.org/10.1117/12.2045647

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