This PDF file contains the editorial “How to Write a Good Scientific Paper: a Reviewer’s Checklist” for JM3 Vol. 14 Issue 02

This PDF file contains the editorial “JM3 2014 List of Reviewers” for JM3 Vol. 14 Issue 02

This PDF file contains the editorial “Special Section Guest Editorial: Control of IC Patterning Variance Part 1: Metrology, Process Monitoring, and Control of Critical Dimension” for JM3 Vol. 14 Issue 02

Patterning based on directed self-assembly (DSA) of block copolymer (BCP) has been demonstrated to be a cost-effective manufacturing technique for advanced sub-20-nm structures. This paper describes the application of Mueller matrix spectroscopic ellipsometry (MMSE) based scatterometry to optically characterize polystyrene-b-polymethylmethacrylate patterns and Si fins fabricated with DSA. A regression-based (inverse-problem) approach is used to calculate the line-width, line-shape, sidewall-angle, and thickness of the DSA structures. In addition, anisotropy and depolarization calculations are used to determine the sensitivity of MMSE to DSA pattern defectivity. As pattern order decreases, the mean squared error value increases, depolarization value increases, and anisotropy value decreases. These specific trends are used in the current work as a method to judge the degree of alignment of the DSA patterns across the wafer.

Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (<0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.

A metrology approach to detect nanoscale asymmetries in structures on a silicon wafer is being introduced through simulation investigations. The simulations were performed based on a rigorous coupled-wave analysis. A structured spot focused on the wafer with a high-numerical aperture (NA=0.7) has been scanned over the wafer. Having access to the complex amplitude of the wavefront over the field, both the intensity and the phase profile of the spot have been investigated in the far-field image plane. To show the proof of concept, we considered a 10-nm asymmetry that appears in the radius of the bottom roundings of a trench on the wafer. The results have been compared to the case of using a conventional spot and it has been shown that the structured illumination provides more sensitivity to the presence of asymmetry. In both illumination cases, the phase distribution along the spot was shown to be more sensitive to the changes due to the presence of asymmetry in the wafer.

A scanning electron microscope (SEM) is the metrology tool used to accurately characterize very fine structures on wafers, usually by extracting one critical dimension (CD) per SEM image. This approach for optical proximity correction (OPC) modeling requires many measurements resulting in a lengthy cycle time for data collection, review, and cleaning, and faces reliability issues when dealing with critical two-dimensional (2-D) structures. An alternative to CD-based metrology is to use SEM image contours for OPC modeling. To calibrate OPC models with contours, reliable contours matched to traditional CD-SEM measurements are required along with a method to choose structure and site selections (number, type, and image space coverage) specific to a contour-based OPC model calibration. The potential of SEM contour model-based calibration is illustrated by comparing two contour-based models to reference models, one empirical model and a second rigorous simulation-based model. The contour-based models are as good as or better than a CD-based model with a significant advantage in the prediction of complex 2-D configurations with a reduced metrology work load.

Early in-line detection of systematic patterning problems in technology development can dramatically improve a technology’s chance for success. By uncovering layout geometries that are difficult to implement, prompt action may be taken so that solutions are in place well before product chips that contain these and similar patterns enter the manufacturing line. If a solution is not in place, this could spell disaster for the product and perhaps even the technology. Ideally, product chips will work on the first lot, which is referred to as “first time right.” To help ensure this, a methodology for in-line detection of systematic patterning problems using E-beam hot spot inspection (EBHI) was developed. We review this methodology, including the latest enhancements. Pattern simulation tools and other sources are used to provide die locations with challenging geometries for evaluation. EBHI evaluates the patterning capability for these locations using modulated wafers. A multifunction team addresses any hot spots that fail within the process window. EBHI is then used to evaluate the solutions proposed by this team. Application of this methodology to a fin-shaped field effect transistor technology is described using examples from the fin and back end of line modules. These examples illustrate the full range of actions used to resolve patterning issues.

A fully automated silicon-based methodology for systematic analysis of electrical features is shown. The system was developed for process monitoring and electrical variability reduction. A mapping step was created by dedicated structures such as static-random-access-memory (SRAM) array or standard cell library, or by using a simple design rule checking run-set. The resulting database was then used as an input for choosing locations for critical dimension scanning electron microscope images and for specific layout parameter extraction then was input to SPICE compact modeling simulation. Based on the experimental data, we identified two items that must be checked and monitored using the method described here: transistor’s sensitivity to the distance between the poly end cap and edge of active area (AA) due to AA rounding, and SRAM leakage due to a too close N-well to P-well. Based on this example, for process monitoring and variability analyses, we extensively used this method to analyze transistor gates having different shapes. In addition, analysis for a large area of high density standard cell library was done. Another set of monitoring focused on a high density SRAM array is also presented. These examples provided information on the poly and AA layers, using transistor parameters such as leakage current and drive current. We successfully define “robust” and “less-robust” transistor configurations included in the library and identified unsymmetrical transistors in the SRAM bit-cells. These data were compared to data extracted from the same devices at the end of the line. Another set of analyses was done to samples after Cu M1 etch. Process monitoring information on M1 enclosed contact was extracted based on contact resistance as a feedback. Guidelines for the optimal M1 space for different layout configurations were also extracted. All these data showed the successful in-field implementation of our methodology as a useful process monitoring method.

Lithographic critical dimension (CD) printing variability can be easily captured with a CD uniformity measurement; however, minimizing the variability is a challenging task that requires manipulation of many variables. Contact hole variability has a direct impact on device performance, while via variability affects metal area scaling and design. Subresolution assist features (SRAFs) have been used in the past to improve lithographic printing variability. SRAFs enhance the image log slope of nearby features but are not intended to print themselves. The role of SRAFs in extreme ultraviolet is explored here.

The perpendicularly orientated lamellar structure of the self-organized diblock copolymer is an attractive template for sub-10-nm line-and-space pattern formation. We propose a method of evaluating the neutral layer (NL) whose performance has an important bearing on the perpendicular orientation of the lamellar structure. The random copolymer of methyl methacrylate and i-butyl POSS methacrylate (MAIBPOSS) has been investigated as an NL for a polymethylmethacrylate-b-polymethacrylethylPOSS (PMMA-b-PMAIBPOSS) lamellar structure. PMMA-b-PMAIBPOSS material has the potential to form sub-10 nm line-and-space pattern, in addition to high etch selectivity due to its POSS structure. Under the free surface, PMMA-b-PMAIBPOSS film on the random copolymer layer showed horizontal orientation. However, a half-pitch of a 7-nm finger pattern structure was observed by peeling off the horizontally oriented layer. The upper portion of the PMMA-b-PMAIBPOSS film was eliminated till proximity of the random copolymer layer by CF₄ gas etching. From the result, it was revealed that the PMMA-r-PMAIBPOSS works as an NL. It was confirmed that the contact angle analysis using an appropriate polymer is a suitable method for evaluation of the surface energy performance of the copolymer with the attribute of high segregation energy.