This PDF file contains the editorial “JM3 Acronyms” for JM3 Vol. 6 Issue 03

This PDF file contains the editorial “Resolution Enhancement Techniques and Design for Manufacturability: Containing and Accounting for Variabilities in Integrated Circuit Creation” for JM3 Vol. 6 Issue 03

As smaller feature sizes and hyper-numerical apertures (>1.0) are approached, rigorous electromagnetic field (EMF) simulation of light diffraction from the mask predicts a more pronounced impact of the mask topography, the optical properties of the mask materials, and the polarization of the incident light on the resulting intensity and the phase of the diffracted light, and on the imaging performance of a lithographic process. This work applies rigorous EMF simulation for the exploration of several aspects of the imaging performance of different binary and 6% attenuated mask stacks at the limits of dry, water immersion, and high index or oil immersion lithography. Several consequences with respect to typical lithographic performance parameters are discussed. The described mask diffraction phenomena have a strong impact on the sensitivity of printed linewidths and process windows with respect to the illumination intensity in the preferred state (IPS) of polarization. Advanced diffraction phenomena are also shown to be important for the lithographic performance of assist features. A new metric, the so-called assist bending efficiency (ABEF), is proposed to quantify the related effects. Modifications of the phase of the diffracted light may result in placement errors and process-window deformations.

An accurate optical model is the foundation of an accurate optical proximity correction (OPC) model, which has always been the key for successful implementation of model-based OPC. As critical dimension (CD) control requirements become severe at the 45- and 32-nm device generations, OPC model accuracy and hence optical model accuracy requirements become more stringent. In previous generations, certain optical effects could be safely ignored. For example, the transmission attenuation particularly at high spatial frequencies caused by lens apodization effects and organic pellicle films was ignored or not accurately modeled in conventional OPC simulators. These effects are now playing a more important role in OPC modeling as technology scales down. Our simulations indicate these effects can cause CD modeling errors of 5 nm or larger, at the 45-nm technology node and beyond. Therefore, they must be accurately modeled in OPC modeling. In our OPC modeling methodology, we propose two novel low-pass-filter models to capture the frequency-dependent transmission attenuation due to lens apodization and to pellicle films. These parameterized novel low-pass-filter models ensure that lens apodization and pellicle-film-induced transmission attenuation can be appropriately account for through regression during the experimental OPC model calibration stage in the case where no measured transmission data are available, thus enabling physics-centric OPC model building with considerably higher accuracy. We can then avoid overfitting the OPC model, which could cause instability in the OPC correction stage. The validity and efficiency of the proposed novel models are also verified using an industry-standard lithography simulator as well as an experimental OPC model calibration at the 45-nm technology node.

Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional model-based OPC assumes nominal process conditions without considering process variations because of the lack of variational lithography models. A simple method to improve OPC results under process variations is to sample multiple process conditions across the process window, which requires long run times. We derive a variational lithography model (VLIM) that can simulate across the process window without much run-time overhead compared to the conventional lithography models. To match the model to experimental data, we demonstrate a VLIM calibration method. The calibrated model has accuracy comparable to nonvariational models, but has the advantage of taking process variations into consideration. We introduce the variational edge placement error (VEPE) metrics based on the model, a natural extension to the edge placement error (EPE) used in conventional OPC algorithms. A true process-variation aware OPC (PVOPC) framework is proposed used the VEPE metric. Due to the analytical nature of VLIM, our PVOPC is only about 2 to 3× slower than the conventional OPC, but it explicitly considers the two main sources of process variations (exposure dose and focus variations) during OPC. Thus our post-PVOPC results are much more robust than the conventional OPC ones, in terms of both geometric printability and electrical characterization under process variations.

With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RETs) such as optical proximity correction (OPC) are an integral part of the design to mask flow. OPC creates complex features to the layout, resulting in mask data volume explosion and increased mask costs. Traditionally, the mask flow has suffered from a lack of design information, such that all features (whether critical or noncritical) are treated equally by RET insertion. We develop a novel minimum cost of correction (MinCorr) methodology to determine the level of correction of each layout feature, such that prescribed parametric yield is attained with minimum RET cost. This flow is implemented with model-based OPC explicitly driven by timing constraints. We apply a mathematical-programming-based slack budgeting algorithm to determine OPC level for all polysilicon gate geometries. Designs adopted with this methodology achieve up to 20% Manufacturing Electron Beam Exposure System (MEBES) data volume reduction and 39% OPC run-time improvement.

We present a semiautomatic procedure for the optimization of lithographic process conditions. In the regime of resolution enhancement techniques such as optical proximity correction, off-axis illumination, and phase shifting masks, the design of lithographic photomasks and illumination sources becomes increasingly intricate. Earlier "what you see is what you get" (WYSIWYG) approaches cannot be applied anymore. Instead, the employment of sophisticated design optimization tools is inevitable. In contrast to related efforts using an inverse problem formulation to address this goal, the approach presented here can be considered a direct method: mask and illumination layouts are mutually altered, evaluated, and improved, using an heuristic search algorithm. Thus, not only does this method require very little a priori knowledge of the process, it also allows for a very flexible problem formulation, enabling an easy integration of different model options or even process steps. As an underlying optimization algorithm of the presented procedure, a genetic algorithm has been used, whose flow, data representation, and basic operations are discussed briefly. Different representation types for both mask and illumination setups and the formulation of the optimization objectives are explained in detail. Various well-performing mask and illumination settings demonstrate the feasibility of the proposed approach and point out further potentials: in contrast to single problem specific approaches, this method is applicable to a great variety of different complex optimization tasks in advanced lithography.

In recent years, design for manufacturability (DFM) has become an important focus item of the semiconductor industry and many new DFM applications have arisen. Most of these applications rely heavily on the ability to model process sensitivity, and here we explore the role of through-process modeling on DFM applications. Several different DFM applications are examined and their lithography model requirements analyzed. The complexities of creating through-process models are then explored, and methods to ensure their accuracy presented.

We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction (pre-OPC) layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC's, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process "hot spots." With this approach, a set of design for manufacturability (DFM) compliance design rules is derived and applied to the product developments for both 90- and 65-nm process technology nodes. Several hot spots in the products (designed with 90-nm design rules) are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope (SEM) images validate the approach.

Variability of electrical parameters across the product die and wafer compromises functionality and yield of integrated device families in the sub-100-nm technologies, such as System-on-Chip. We discuss variability reduction through: Tightening manufacturing process variability, design-for-manufacturability (DFM) rules, and parameterized, correct-by-construction (CBC) layout. While so far the best option for variability reduction has been to improve process capability without impacting product design, it may no longer be preferred due to continuously increasing processes cost driven by technology shrinks. Currently, the CBC parametric layout emerges as the best option, with parametric variability traded for device footprint or the aggressiveness of the resolution enhancement techniques [e.g., optical proximity correction (OPC)]. The least favorable from the product flow standpoint is the layout-time addition of design rules or OPC in response to the localized issues in a random layout (hot spots), which causes reworks and delays, or compromises the process window. For the optimal parameterized layout, we discuss rule development for MOSFET gate length variation and dummy device placement. In summary, a number of tradeoffs are necessary for the design optimization to minimize device variability, depending on the product application.

Hot-spot clearance using process simulation is indispensable for low-k₁ lithography processes. Hot spots will occur mainly depending on local pattern context. Appropriate calibration of design rules, mask data preparation, resolution enhancement techniques, and optical proximity effect correction will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of the design at the hot spot will be effective, but it takes too much time. Therefore, there is a need for an automated hot-spot fixing system so as to avoid fatal hot-spot occurrence, with sufficient process margins and short turnaround time. We developed an automated hot-spot fixing system, the hot-spot fixer (HSF). Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. We applied the HSF system to the metal layer of logic devices of 65 nm and most of the hot spots were diminished throughout a full chip within 12 hours. Thus, HSF feasibility has been proved for metal layers in the 65-nm node and below with full-chip data volume.

In the past, complying with design rules was sufficient to ensure acceptable yields for a design. However, for sub-100-nm designs, this approach tends to create patterns that cannot be reliably printed for a given optical setup, thus leading to hot spots and systematic yield failures. Recent challenges faced by both the design and process communities call for a paradigm shift whereby circuits are constructed from a small set of lithography-friendly patterns that have previously been extensively characterized and ensured to print reliably. We describe the use of a regular design fabric for defining the underlying layout geometries of the circuit. While the direct application of this methodology to the current application-specific integrated circuit (ASIC) design flow would result in unnecessary area and performance penalties, we overcome these penalties via a unique design flow that ensures shape-level regularity by reducing the number of required logic functions as much as possible as part of the top-down design flow. We show that with a small set of Boolean functions and careful selection of lithography-friendly patterns, we not only mitigate but essentially eliminate such penalties. Additionally, we discuss the benefits of using extremely regular designs constructed from a limited set of lithography-friendly patterns not only to improve manufacturability but also to relax the pessimistic constraints defined by design rules. Specifically, we introduce the basis to exploit the regularity in the layout patterns by using “pushed-rules” for logic design, as is commonly done for static random access memory (SRAM). This in turn facilitates a common optical proximity correction (OPC) methodology for logic and SRAM. Moreover, by taking advantage of this newfound manufacturability and predictability of regular circuits, we show that the performance of logic built on regular fabrics can surpass that of seemingly more arbitrarily constructed logic.

After the successful results obtained in the last few years, electron beam direct write (EBDW) lithography for use in integrated circuit manufacturing has now been demonstrated. However, throughput and resolution capabilities need to be improved to push its interest for fast cycle production and advanced research and development applications. In this way, the process development needs good patterns dimensional accuracy, i.e., a better control of the proximity effects caused by backscattering electrons and others phenomenon. In this work, the limitations of the dose modulation method are investigated through the change of dose number steps and the use of a more accurate point spread function. To continue reducing feature sizes, a method to provide a complementary correction to the dose modulation solution is proposed. This rule-based electron beam proximity correction, or REBPC, provides good results down to 40 nm.

A versatile photolithographic photoplotter based on a standard photoreduction stepper, where the reticle is replaced by a commercial liquid crystal microdisplay, is reported. The microdisplay module is designed as a drop-in replacement, allowing the photoplotter to be simply and quickly converted into a standard stepper, making it an extremely versatile, low-cost research and development tool. Binary and multilevel plotting are demonstrated with plot rates of several Mpixels/s and 1-μm feature sizes into standard industrial photoresist. The limitations on plot rate and resolution are presented and techniques for overcoming them discussed.

Cycloalkanes are candidates for immersion fluids because of their potential for low absorption in the 193-nm region and for a high refractive index (RI). We have developed an empirical correlation between refractive index and density of alkanes, which allows a prediction of the best candidates for immersion fluids based on the alkane structure. In particular, the correlation reveals that polycycloalkanes such as perhydrophenanthrene (PHPh) and perhydrodropyrene (PHPy), which have a higher RI than linear or cyclic alkanes, will be excellent candidates for immersion fluids at 193 nm. Therefore, PHPh and PHPy were synthesized by exhaustive hydrogenation of phenanthrene and pyrene. However, methods for the purification of the synthesized and commercial alkanes such as cyclodecane (CYD), cyclohexane (CYX), pentane (PNT), and decalin (DEC) are required in order to determine the actual absorption of candidates at 193 nm. The presence of an absorbing impurity at 193 nm can cause the premature elimination of otherwise excellent potential candidates. A rather subtle impurity is molecular oxygen, which does not itself absorb at 193 nm, but which forms complexes with alkanes that do absorb at 193 nm. In this case, the "impurity" is readily eliminated by simple purging with nitrogen or argon gas.

In the dip pen nanolithography (DPN) process, ultra-sharp scanning probe tips ("pens") are coated with chemical compounds (or "ink") and contacted with a surface to produce submicron-sized features. This work describes the design, fabrication, and testing of a microfluidic ink delivery device for delivering multiple species of inks to an array of multiple pens, as well as for maximizing the number of inks for simultaneous patterning by DPN. The microfluidic device (called "Centiwell") consists of a 2-D array of 96 microwells that are obtained by silicon bulk micromachining process. A thermoelectric module is attached to the bottom of the substrate. Microbeads of a hygroscopic material (e.g., polyethylene glycol or PEG) are dispensed into the microwells. The thermoelectric module cools the substrate to below the dew point for condensing water droplets on the microbeads and to create PEG solutions that serve as the ink for DPN. An array of pens is then coated with the ink. Subsequently, nanolithography is performed with the coated pens. Multiple PEG nanopatterns obtained by this method are presented as proof-of-concept. This demonstrates the functionality of the Centiwell microfluidic ink delivery device for nanolithography of multiple inks. Also, fractal nanopatterns are observed in the nanolithography experiments.

Emulation of phase-shift mask (PSM) imaging techniques through the use of acousto-optic interaction, rather than fixed photomasks, is demonstrated. The phasefront and irradiance profile of a uniform illumination beam are manipulated acousto-optically in two dimensions by controlling the phase and amplitude of the radio-frequency (RF) signals, which drive the acousto-optic modulators used as the basis for these investigations. Enhancements in aerial image resolution and edge slope are shown by contrasting image quality for nonphase-shifted features against features patterned using acousto-optic emulation of alternating phase-shift mask, attenuated phase-shift mask, and chromeless phase-shift mask imaging techniques. A demonstration of vortex via patterning is also shown to highlight the versatility of this technique in creating complex two dimensional patterns. An overview of the experimental method and hardware is presented along with the results.

We present the details of our study on the internal stresses and adhesion strengths of SU-8 structures to different substrate seed layers. The effect of adhesion promoter—methacryloxy [propl] trimethoxysilane (MPTS), and OmniCoat—and different seed layer combinations (Ti/Cu/Ti, Ti/Cu, Cr/Au, and Cr/Au/Cr) was examined for internal stress and adhesion strength in 650-μm-thick SU-8 films. Increased stress and poor adhesion have led to the delamination of SU-8 in some cases. Adhesion and stress have proven to be the function of process parameters such as soft bake (time and temperature), exposure dose, post-exposure bake (time and temperature), and development time. We have found that a <100> silicon wafer containing a titanium-copper-titanium (Ti/Cu/Ti) seed layer with MPTS as the adhesion promoter yielded a thick SU-8 film with a lower value of stress and consequently better adhesion for processing in deep x-ray lithography (DXRL). A detailed correlation of the effects of adhesion and internal stress on the SU-8 film is discussed. An analysis of the possible chemical bonding interactions occurring between SU-8, and its adhesion promoter and/or substrate is also presented.

We report the influence of bonding temperature on SU-8 to SU-8 bonding and report fabrication of a hybrid microelectromechanical-tunable filter (MEM-TF) using SU-8 bond pads. We demonstrate use of 2-μm-thick 50×50-μm² SU-8 bond pads to attach 4.92-μm-thick 250×250-μm² Al_0.4Ga_0.6As-GaAs distributed Bragg reflectors (DBR) to polysilicon MUMPs^® piston actuators. Advantages of this process include compatibility with hydrofluoric-acid-release chemistry, low-temperature/low-pressure bonding, simple bond-pad photolithography, 57% flip-bonded DBR yield, and 30% electrostatically actuatable hybrid MEM-TF yield.

We present an innovative micro gyroscope that is capable of detecting three-dimensional (3-D) angular motions. The motion of each sensing element is, by mechanical design, restricted to move in a direction orthogonal to each other such that measurements by high-resolution capacitors with signal processing circuits are decoupled and precisely represent, to some extent, angular velocity components in three axes. In order to ensure better repeatability and more reliability, the suspension flexures and stiffness are studied such that the stress of the proposed micro gyroscope is reduced, but the stroke of angular displacements is increased. Owing to the complicated geometry of the suspension flexures, the finite element method (FEM) is employed to obtain more exact stiffness value and compared with theoretical analysis. The dynamic model of the proposed gyroscope is established to include nonlinear terms and gyroscopic effects. The entire micro device can be produced merely by surface micromachining and wet etching such that the mass production cost has been considered at the design stage but the resolution, bandwidth, and decoupling capability of tri-axis detection are expected to be enhanced.

A new approach has been developed to fabricate a low-voltage integrated electrophoresis chip based on silicon-on-insulator micro electron mechanical systems (SOI-MEMS). Arrayed-electrodes are embedded along the microchannel sidewall in the designed microchip. Because voltage should be applied effectively to arrayed-electrodes to serve as the driving force for the on-microchip electrophoresis, electrical isolation between arrayed-electrodes is essential for a practicable low-voltage integrated electrophoresis chip. Fabrication of arrayed-electrodes becomes the critical technique that governs the performance of the low-voltage integrated electrophoresis chip. Combined with the SOI substrate, full dielectric isolation is proposed to obtain high-performance integrated three-dimensional (3-D) sidewall arrayed-electrodes. The fabrication processes mainly consist of SOI wafer fabrication, narrow trench etching, polysilicon refilling and planarization, boron diffusion to form arrayed-electrodes, elicitation and protection of arrayed-electrodes, dry etching to obtain reservoirs and microchannels, etc. In order to obtain high-quality electrical isolation between arrayed-electrodes, process experiments were conducted to obtain optimized operational parameters. Poly (dimethylsiloxane) (PDMS) was selected as a cover to achieve a hybrid electrophoresis chip. The validity of the hybrid electrophoresis chip was tested by amino acid separation. Results showed high performance of the fabricated low-voltage integrated electrophoresis chip based on SOI-MEMS.

The interdisciplinary nature of optical microelectromechanical systems (MEMS) makes its design a highly involved process. To design a device that will meet the required specifications over its entire lifetime, reliability issues must be included in the design process. This work develops a method that can be used to create a step-by-step design process involving reliability issues at every stage. The process begins by listing out the constants and constraints of the design. Taking all such constraints into account, an optical design process is outlined. The effect of individual errors is studied on a key parameter like insertion loss. This gives the designer information about which parameters the design is more sensitive to, and will help in deciding the manufacturing tolerances required in the different stages. Using all of these data, an "ideal design" is developed. A Monte Carlo analysis is carried out on that design to show the effect of errors occurring simultaneously. The work concludes with a flow chart of a suggested design process to be used when designing optical MEMS devices.

It is convenient to characterize thin film material properties using commercially available nanoindentation systems. This study aims to discuss several considerations while determining the thin film elastic modulus by means of a microcantilever bending test using a commercial nanoindentation system. The measurement results are significantly improved after: 1. the indentation of the film during the test is considered and corrected, and 2. the boundary effects are considered in the model by finite element method. In application, the elastic modulus of electroplating nickel film 11 μm thick was characterized.