Special Section on Advanced Plasma-Etch Technology

Double patterning with dual hard mask for 28-nm node devices and below

[+] Author Affiliations
Hubert Hody, Vasile Paraschiv, Emma Vecchio, Sabrina Locorotondo, Gustaf Winroth, Raja Athimulam, Werner Boullart

IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

J. Micro/Nanolith. MEMS MOEMS. 12(4), 041306 (Oct 01, 2013). doi:10.1117/1.JMM.12.4.041306
History: Received April 11, 2013; Revised August 14, 2013; Accepted August 28, 2013
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Abstract.  A double patterning process resulting in amorphous silicon (a-Si) gate lines with a thickness of 80 nm and a lateral critical dimension <30nm is reported. A full stack for a double patterning approach for etch transfer down to an Si layer, including a hard mask (HM) in which the line and cut patterning are performed, is presented. The importance of the HM in the success or failure of the exercise is evidenced. Once the suitable HM has been selected, the etch chemistry is shown to have a significant impact on the line width roughness (LWR) of the gate. Ultimately, remarkably low LWR could be achieved on gates exhibiting a straight profile. All the results shown in this paper have been obtained on 300-mm wafers.

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© 2013 Society of Photo-Optical Instrumentation Engineers

Citation

Hubert Hody ; Vasile Paraschiv ; Emma Vecchio ; Sabrina Locorotondo ; Gustaf Winroth, et al.
"Double patterning with dual hard mask for 28-nm node devices and below", J. Micro/Nanolith. MEMS MOEMS. 12(4), 041306 (Oct 01, 2013). ; http://dx.doi.org/10.1117/1.JMM.12.4.041306


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